Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.
In some existing 3D memory devices, such as 3D NAND memory devices, the memory cell array includes multiple strings of transistors. Each of these strings typically includes at least one row select transistor, multiple memory cell transistors, and one ground select transistor that are connected in series with each other. The source region of the ground selection transistor is electrically connected to a common source line (CSL). The CSL connecting structure is generally formed by depositing metal tungsten into a common source contact hole. Due to the high stress of the metal tungsten, the stress of the 3D NAND memory device may not be even, resulting in various serious process problems, such as wafer warpage, lithography defocusing, cladding misalignment, etc. that are induced by the wafer sliding during the fabricating process.